1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of forming shallow trench isolation (STI) in a semiconductor device.
2. Description of Related Art
An isolation structure, such as a shallow trench isolation structure, is introduced to prevent adjacent metal oxide semiconductor devices from short circuit occurring. A traditional method of forming a shallow trench isolation structure in a substrate is an anisotropic dry etching process. The formed trenches are filled with oxides, by which isolation regions for devices are formed.
A conventional method tor fabricating a trench isolation structure is illustrated as followed.
Referring to FIG. 1A, a pad oxide layer 12 with thickness of about 100.about.500 .ANG. and a silicon nitride layer 14 with thickness of about 1000.about.3000 .ANG. are sequentially formed on a substrate 10. The silicon nitride layer 14 above the pad oxide layer 12 is formed by, for example chemical vapor deposition (CVD). Next, the silicon nitride layer 14 is patterned by a photolithography process and an anisotropic etching process to define trenches. An etching process, such as an anisotropic etching process, is performed upon the substrate 10 using the silicon nitride layer 14 as a mask, in which a trench 15 with depth of about 3000.about.10000 .ANG. is formed therein. Then, an insulating layer 16. such as a silicon dioxide layer, is deposited over the substrate 10 and the trench 15 is filled therewith.
Next, referring to FIG. 1B, the insulating layer 16 is polished by, for example, chemical mechanical polishing (CMP), and insulating plugs 16a are formed in the substrate 10 to be used for trench isolation. After the substrate 10 is performed by a CMP process a phenomenon of micro-scratch occurs on the surface of the insulating layer 16. Therefore referring to FIG. 1C, the substrate 10 is placed in a furnace to be performed by a furnace annealing process, by which the insulating layer 16 and the silicon nitride layer 14 are densified. The phenomenon of micro-scratch is therefore relieved in the later polishing process.
According to the above-described method for fabricating a STI structure, a detail description is illustrated in FIG. 2. At first, a pad oxide is formed on a substrate and a silicon nitride layer is then formed on the pad oxide layer. Then, using the silicon nitride layer as a mask trenches are formed by etching. The trench is filled with oxide by depositing an oxide layer on the substrate. The oxide layer is polished by CMP, by which only a portion of the oxide layer is left in the trench. Next, a furnace annealing process is performed on the substrate to densify the oxide layer and the silicon nitride layer, by which occurrence of micro-scratch is reduced in the later polishing process.
There are some drawbacks in the conventional method for trench isolation. It takes too much time for the furnace annealing process in the furnace. As well known, slurry used in CMP process contains mobile ions, such as potassium ion (K.sup.+) or sodium ion (Na.sup.+), that are left on the substrate. In case of performing a furnace annealing process for a long, time, the mobile ions are quickly diffused into the substrate and makes devices fail.